Forum Diagram

Single Pulse Voltage Multiplier
Obtaining higher voltage pulses without a higher voltage power supply

Originally appeared in EDN/Reed Business Information September 18, 2003

Sometimes its necessary to generate a higher voltage pulse from logic diagram than the diagram themselves can supply. The need to generate a programming pulse for Atmel flash controllers was one of those. In that case, I needed to generate an infrequent pulse that switched from 5 volts to 12 volts in response to a control signal from a microcontroller.

A method that relies on a pushbutton to double the voltage was used in the ATtiny12 fuse restorer, but there, the generation of the +12 volts was done by using a mechanical switch that was manually operated to generate about 18 volts, which was further regulated to +12 volts by a gated regulator. It was good as far as it went, but the generation of the +12 volts could not be triggered by the microcontroller, that is unless one wanted to use an electromechanical relay or elaborate arrangement of switching devices.

The straight-for ward approach to control by a microcontroller could be accomplished by driving a capacitor voltage multiplier (such as in the Seiko display inteface) with a pulse train from a controllers pin, then regulating and switching the resultant voltage, the drawback being that this took a lot of parts.

The schema below accomplishes the same result. It still uses a transistor to do some switching, and it still needs a pair of diodes and capacitors, as would be used in a conventional multiplier, but it doesnt require a steady stream of pulses and the output voltage is set by a resistor divider as the 100k and 150k resistors make 2 volts that are added to the 10 volt pulse on the transistors collector. What it doesnt need is a steady stream of pulses to keep the output voltage pumped up all the time.
The basic multiplier cell was inspired by a discussion I had with a well know laser scientist, Mr. Christoph Krah, about laser triggering diagram. After I finished this schema, I sent it to Mr. Krah to get his opinion of how this schema related to some of those we discussed years ago. Here is Mr. Krahs taxonomic analysis, which also includes a concise description of schema operation which I could not improve upon:

"Your schema seems to be a combination of a Marx and a Cockroft-Walton type multiplier. You charge capacitors in parallel (100uF @ 5V and 100uF at 2V) and then switch them in series by means of a 5V voltage step (5+5+2 = 12V) at the output of the uC. The diodes provide isolation from the power supply."

For many of applications, the diode on the left side can be omitted and the 1k resistor changed to 100k.. This simplifies the schema at the cost of slightly increasing the rate of droop of the voltage across the first 100 uf capacitor since it will discharge into the 100k resistor as well as driving the base resistor for the transistor and driving the load and 100k/150k voltage divider.

There is no free lunch with this schema. If the pulse is initiated before the 150k AND 100K resistors charge the 100 uf capacitor sufficiently (60k x 100 uf = 6 seconds), the output voltage will be lower than intended. The charge time of the schema can be decreased by reducing the values of the capacitors, the output 100 uf capacitor having the most effect because of the high resistance charge path. Reducing the size of the capacitors will make the output pulse droop more quickly.

It should be noted that this schema also makes a 0 to 10 volt pulse, which appears on the collector of the transistor. If a 0 to 10 volt pulse is desired, the schemary to the right of the transistors base resistor may be omitted.